1. Field of the Invention
The present invention is generally directed to the field of manufacturing semiconductor devices, and, more particularly, to methods of forming contact openings.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to increase the operating speed of the transistors, as well as integrated circuit devices incorporating such transistors.
Recently, various stress engineering techniques have been employed in an effort to increase transistor performance. For example, establishing a tensile stress in the channel region of an NMOS transistor can improve the mobility of electrons through the channel. Similarly, by establishing a compressive stress in the channel region of a PMOS transistor, the mobility of holes may be improved, thereby enhancing the performance of the PMOS transistor. Various techniques are used to induce such stresses in the channel regions of transistors. One technique generally involves the deposition of layers of material specifically designed to induce the desired stress within the channel region of the transistors. The manners in which the desired stress conditions may be established in such layers are well known to those skilled in the art.
A typical integrated circuit device will have both NMOS and PMOS transistors. This is particularly true for CMOS applications. Establishing the desired stresses in the channel regions of these different types of transistors can involve many difference process flows in which layers are formed and then partially or completely removed. In some cases, layers of material that induce different types of stress (tensile, compression) are formed on or above one another so as to effectively cancel out or reduce the net stress induced by the combination of both layers.
While the formation of such stress inducing layers can increase device performance, the formation of such layers can also create other problems as it relates to other aspects of manufacturing an integrated circuit. As is well known to those skilled in the art, after a functioning device, e.g., a transistor, a resistor, a capacitor, etc., is formed, electrical contacts are formed so that the device can be electrically coupled to other parts of the integrated circuit and thereby perform its intended function. In modern devices, such electrical connections are established in multiple layers of conductive lines and vias (so-called “metal layers”). For example, a typical microprocessor device may have seven or more layers of conductive lines and vias to establish the conductive interconnections for the microprocessor device.
The process of forming conductive interconnects typically involves, among other things, forming an opening through a layer of material formed above the underlying device or structure to which it is designed to make electrical connection. FIG. 1 provides an illustrative example of a line of polysilicon 10 (field poly) formed above a substrate 12. Also depicted in FIG. 1 is a first protective layer 14, a second protective layer 15, a first stress inducing layer 16, and a second stress inducing layer 18. The protective layers 14, 15 may be comprised of, for example, silicon dioxide. The purpose of the protective layers 14, 15 is to protect the surface of the substrate 12. The protective layers 14, 15 may also act as an etch stop layer when patterning the first and/or second stress inducing layers 16, 18.
In the depicted example, the stress inducing layers 16, 18 are provided to induce a stress within a region of the substrate 12 that will act as a channel region for one or more transistors (not shown). In some cases, the stress inducing layers 16, 18 may be employed to introduce a desired stress condition in either the source region or drain region (or both) of a transistor. For example, the first stress inducing layer 16 may be used to establish a tensile stress within underlying portions of the substrate 12, whereas the second stress inducing layer 18 may be used to establish a compressive stress condition within underlying portions of the substrate 12. The manner in which such stress inducing layers are formed are well known to those skilled in the art. Such stress inducing layers 16, 18 may be comprised of a variety of materials, such as silicon nitride or the like, and they may be formed by a variety of processes, e.g., a plasma enhanced deposition process. Each of the layers 16, 18 may have a thickness ranging from approximately 500-1000 Å.
Ultimately, a conductive connection will have to be formed to the illustrative polysilicon line 10 depicted in FIG. 1. However, due to the large thickness or height of the layer stack 19 produced by the combination of the first and second stress inducing layers 16, 18, and perhaps the protective layers 14, 15, forming an opening through such a layer stack 19 can be difficult and time-consuming. For example, in the case where both of the layers 16, 18 are made of silicon nitride, a very long etching process may be required to etch through the combined thickness of the layers 16, 18, e.g., a combined thickness that may be on the order of approximately 1000-2000 Å. In addition to the long duration of the etching process, such an extended etching process may have other implications, e.g., it may require the formation of protective layers or masks having additional thickness in other areas of the substrate.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.